- Document
- KFO-001
- Revision
- Rev A
- Status
- Ongoing
- Type
- Updated
A small AI accelerator
A compact INT8 neural network inference accelerator in Verilog, verified bit-exactly and headed for an FPGA and Tiny Tapeout.
Problem
Neural networks spend most of their time multiplying and adding numbers. General-purpose processors can do this, but dedicated hardware does it faster and with far less energy. I want to understand that trade-off by building one myself, at a small scale.
Approach
A compact INT8 inference accelerator for handwritten-digit classification: a multiply-accumulate (MAC) datapath, a control state machine, ReLU activation and an argmax output stage. The RTL is verified bit-exactly against a Python reference model with cocotb.
Plan
- Architecture and block diagram
- RTL for the MAC datapath, control and activation
- Bit-exact verification against the Python model
- Running on a low-cost FPGA board
- Comparing variants (weight bit-width, serial vs. parallel MAC) on area, timing and accuracy before a Tiny Tapeout submission
This page is updated as each stage is completed; changes are listed in the revision history below.
Revision history
| Rev A | Project page and plan |